Last date for submission of paper: 08-Oct-2019; Contact person: Dr.D.Gracia Nirmala Rani; The aim of this workshop is to provide hands-on experience on the state -of-the-art Cadence EDA tools for VLSI Design. The participants will have an exposure to the Circuit Design & Simulation, Layout, Physical Verification (DRC, LVS), and Extraction. The workshop includes practice sessions on the C